#ifndef RF_H_
#define RF_H_

/// RF front end block (RF)

#include "Generic/Peripheral/Peripheral.h"

/// Registers definition
enum
{
    REG_RF_IDCODE = 0x4/4,
    REG_RF_RESET,
    REG_RF_REG3,
    REG_RF_REG4,
    REG_RF_REG5,
    REG_RF_REG6,
    REG_RF_REG7,
    REG_RF_REG8,
    REG_RF_REG9,
    REG_RF_REGA,
    REG_RF_REGB,
    REG_RF_REGC,
    REG_RF_REGD,
    REG_RF_REGE,
    REG_RF_REGF,
    REG_RF_REG10,
    REG_RF_REG11,
    REG_RF_REG12,
    REG_RF_REG13,
    REG_RF_REG14,
    REG_RF_REG15,
    REG_RF_REG16,
    REG_RF_REG17,
    REG_RF_REG18,
    REG_RF_REG19,
    REG_RF_REG1A,
    REG_RF_REG1B,
    REG_RF_REG1C,
    REG_RF_REG1D,
    REG_RF_REG1E,
    REG_RF_REG1F,
    REG_RF_REG20,
    REG_RF_REG21,
    REG_RF_REG22,
    REG_RF_REG23,
    REG_RF_REG24,
    REG_RF_REG25,
    REG_RF_REG26,
    REG_RF_REG27,
    REG_RF_REG28,
    REG_RF_REG29,
    REG_RF_REG2A,
    REG_RF_REG2B,
    REG_RF_REG2C,
    REG_RF_REG2D,
    REG_RF_REG2E,
    REG_RF_REG2F,
    REG_RF_REG30,
    REG_RF_REG31,
    REG_RF_REG32,
    REG_RF_REG33,
    REG_RF_REG34,
    REG_RF_REG35,
    REG_RF_REG36,
    REG_RF_REG37,
    REG_RF_REG38,
    REG_RF_REG39,
    REG_RF_REG3A,
    REG_RF_REG3B,
    REG_RF_REG3C,
    REG_RF_REG3D,
    REG_RF_REG3E,
    REG_RF_REG3F,
    REG_RF_PLL_VAL = 0x104/4,
    REG_RF_CLK_CTL,
    REG_RF_PWR_CTL,
    REG_RF_PU_OVR0,
    REG_RF_PU_OVR_VAL0,
    REG_RF_PU_OVR1,
    REG_RF_PU_OVR_VAL1,
    REG_RF_RX_GAIN_OVR,
    REG_RF_RF_PLL_TX_BASE0,
    REG_RF_RF_PLL_TX_BASE1,
    REG_RF_RF_PLL_TX_BASE2,
    REG_RF_RF_PLL_TX_DELTA0,
    REG_RF_RF_PLL_TX_DELTA1,
    REG_RF_RF_PLL_RX_BASE0,
    REG_RF_RF_PLL_RX_BASE1,
    REG_RF_RF_PLL_RX_BASE2,
    REG_RF_RF_PLL_RX_DELTA0,
    REG_RF_RF_PLL_RX_DELTA1,
    REG_RF_VCO_LUT_ADDR,
    REG_RF_VCO_LUT_DATA_IN0,
    REG_RF_VCO_LUT_DATA_IN1,
    REG_RF_PLL_OFFSET = 0x160/4,
    REG_RF_IFP_INT,
    REG_RF_IFP_FRACT0,
    REG_RF_IFP_FRACT1,
    REG_RF_TR_CTRL0,
    REG_RF_TR_CTRL1,
    REG_RF_R_RSSI = 0x208/4,
    REG_RF_R_REG3,
    REG_RF_R_REG4,
    REG_RF_R_REG5,
    REG_RF_R_REG6,
    REG_RF_R_REG7,
    REG_RF_R_REG8,
    REG_RF_R_REG9,
    REG_RF_R_REGA,
    REG_RF_R_REGB,
    REG_RF_R_REGC,
    REG_RF_R_REGD,
    REG_RF_R_REGE,
    REG_RF_R_REGF,
    REG_RF_R_REG10,
    REG_RF_R_REG11,
    REG_RF_R_REG12,
    REG_RF_R_REG13,
    REG_RF_R_REG14,
    REG_RF_R_REG15,
    REG_RF_R_REG16,
    REG_RF_R_REG17,
    REG_RF_R_REG18,
    REG_RF_R_REG19,
    REG_RF_R_REG1A,
    REG_RF_R_REG1B,
    REG_RF_R_REG1C,
    REG_RF_R_REG1D,
    REG_RF_R_REG1E,
    REG_RF_R_REG1F,
    REG_RF_R_REG20,
    REG_RF_R_REG21,
    REG_RF_R_REG22,
    REG_RF_R_REG23,
    REG_RF_R_REG24,
    REG_RF_R_REG25,
    REG_RF_R_REG26,
    REG_RF_R_REG27,
    REG_RF_R_REG28,
    REG_RF_R_REG29,
    REG_RF_R_REG2A,
    REG_RF_R_REG2B,
    REG_RF_R_REG2C,
    REG_RF_R_REG2D,
    REG_RF_R_REG2E,
    REG_RF_R_REG2F,
    REG_RF_R_REG30,
    REG_RF_R_REG31,
    REG_RF_R_REG32,
    REG_RF_R_REG33,
    REG_RF_R_REG34,
    REG_RF_R_REG35,
    REG_RF_R_REG36,
    REG_RF_R_REG37,
    REG_RF_R_REG38,
    REG_RF_R_REG39,
    REG_RF_R_REG3A,
    REG_RF_R_REG3B,
    REG_RF_R_REG3C,
    REG_RF_R_REG3D,
    REG_RF_R_REG3E,
    REG_RF_R_REG3F,
    REG_RF_R_PLL_VAL = 0x304/4,
    REG_RF_R_CLK_CTL,
    REG_RF_R_PWR_CTL,
    REG_RF_R_PU_OVR0,
    REG_RF_R_PU_OVR_VAL0,
    REG_RF_R_PU_OVR1,
    REG_RF_R_PU_OVR_VAL1,
    REG_RF_R_RX_GAIN_OVR,
    REG_RF_R_RF_PLL_TX_BASE0,
    REG_RF_R_RF_PLL_TX_BASE1,
    REG_RF_R_RF_PLL_TX_BASE2,
    REG_RF_R_RF_PLL_TX_DELTA0,
    REG_RF_R_RF_PLL_TX_DELTA1,
    REG_RF_R_RF_PLL_RX_BASE0,
    REG_RF_R_RF_PLL_RX_BASE1,
    REG_RF_R_RF_PLL_RX_BASE2,
    REG_RF_R_RF_PLL_RX_DELTA0,
    REG_RF_R_RF_PLL_RX_DELTA1,
    REG_RF_R_VCO_LUT_ADDR,
    REG_RF_R_VCO_LUT_DATA_IN0,
    REG_RF_R_VCO_LUT_DATA_IN1,
    REG_RF_R_VCO_LUT_DATA_OUT0,
    REG_RF_R_VCO_LUT_DATA_OUT1,
    REG_RF_R_PLL_OFFSET,
    REG_RF_R_IFP_INT,
    REG_RF_R_IFP_FRACT0,
    REG_RF_R_IFP_FRACT1,
    REG_RF_R_TR_CTRL0,
    REG_RF_R_TR_CTRL1,
    REG_RF_R_REG60 = 0x380/4,
    REG_RF_R_REG61,
    REG_RF_R_REG62,
    REG_RF_R_REG63,
    REG_RF_R_REG64,
    REG_RF_R_REG65,
    REG_RF_R_REG66,
    REG_RF_R_REG67,
    REG_RF_R_REG68,
    REG_RF_R_REG69,
    REG_RF_R_REG6A,
    REG_RF_R_REG6B,
    REG_RF_R_REG6C,
    REG_RF_R_REG6D,
    REG_RF_R_REG6E,
    REG_RF_R_REG6F,
    REG_RF_MODEM_IDCODE = 0x404/4,
    REG_RF_GAINLUT0,
    REG_RF_GAINLUT1,
    REG_RF_GAINLUT2,
    REG_RF_GAINLUT3,
    REG_RF_GAINLUT4,
    REG_RF_GAINLUT5,
    REG_RF_GAINLUT6,
    REG_RF_GAINLUT7,
    REG_RF_GAINLUT8,
    REG_RF_AGCCTRL0,
    REG_RF_AGCCTRL1,
    REG_RF_AGCSTATUS,
    REG_RF_RSSIDCSTATUS,
    REG_RF_SQUELCHCTRL,
    REG_RF_RXPSKCTRL0,
    REG_RF_RXPSKCTRL1,
    REG_RF_DCOFFESTCTRL0,
    REG_RF_DCOFFESTCTRL1,
    REG_RF_DCOFFESTCTRL2,
    REG_RF_DCOFFESTCTRL3,
    REG_RF_DCOFFESTCTRL4,
    REG_RF_DCOFFESTCTRL5,
    REG_RF_DEMODCTRL,
    REG_RF_SYNCCTRL,
    REG_RF_EQCOEFFCTRL0,
    REG_RF_EQCOEFFCTRL1,
    REG_RF_LOOPCOEFFCTRL0,
    REG_RF_LOOPCOEFFCTRL1,
    REG_RF_PSKSYNCWORD0,
    REG_RF_PSKSYNCWORD1,
    REG_RF_PSKSYNCWORD2,
    REG_RF_ADJFCCTRL,
    REG_RF_IFFREQ,
    REG_RF_DCOFFCOMPQ,
    REG_RF_DCOFFCOMPI,
    REG_RF_MODCTRL0,
    REG_RF_MODCTRL1,
    REG_RF_LOOPCOEFFCTRL2,
    REG_RF_LOOPCOEFFCTRL3,
    REG_RF_TXQPSKLUTCTRL = 0x4ac/4,
    REG_RF_TX8PSKLUTCTRL0,
    REG_RF_TX8PSKLUTCTRL1,
    REG_RF_TSSICTRL,
    REG_RF_TSSISTATUS,
    REG_RF_TESTCTRL,
    REG_RF_PA_VCTRL_CTRL,
    REG_RF_TXPUCTRL,
    REG_RF_RXPUCTRL,
    REG_RF_SYNTHPUCTRL,
    REG_RF_PARAMPCTRL = 0x4d8/4,
    REG_RF_VCOLOPUCTRL,
    REG_RF_DSADCPUCTRL,
    REG_RF_TRPUCTRL,
    REG_RF_TSSIPUCTRL,
    REG_RF_CLKCTRL = 0x4f0/4,
    REG_RF_RXPSKCTRL2,
    REG_RF_RXPSKCTRL3,
    REG_RF_RXPSKCTRL4,
    REG_RF_AGCCTRL2,
    REG_RF_REVISION,
    REG_RF_DCOFFCOMPQ1,
    REG_RF_DCOFFCOMPI1,
    REG_RF_DCOFFCOMPQ2,
    REG_RF_DCOFFCOMPI2,
    REG_RF_DCOFFCOMPQ3,
    REG_RF_DCOFFCOMPI3,
    REG_RF_DCOFFCOMPQ4,
    REG_RF_DCOFFCOMPI4,
    REG_RF_IQCOMP1,
    REG_RF_IQCOMP2,
    REG_RF_IQCOMP3,
    REG_RF_IQCOMP4,
    REG_RF_RXPSKPHERR1,
    REG_RF_RXPSKPHERR2,
    REG_RF_RXPSKPHERR3,
    REG_RF_RXPSKPHERR4,
    REG_RF_RXPSKPHERR5,
    REG_RF_RXPSKPHERR6,
    REG_RF_RXPSKMAGERR,
    REG_RF_SLNA_GAINLUT0,
    REG_RF_SLNA_GAINLUT1,
    REG_RF_SLNA_CTRL0,
    REG_RF_SLNA_CTRL1,
    REG_RF_SWP_STARTKICK,
    REG_RF_SWP_ENDINC,
    REG_RF_SWP_THRESH,
    REG_RF_SWP_COUNTER,
    REG_RF_SWP_VCOCALCAP,
    REG_RF_SWP_THRESHRSSI,
    REG_RF_SWP_SPECVAL0,
    REG_RF_SWP_SPECVAL1,
    REG_RF_SWP_SPECVAL2,
    REG_RF_SWP_SPECVAL3,
    REG_RF_SWP_SPECVAL4,
    REG_RF_SWP_SPECVAL5,
    REG_RF_SWP_SPECVAL6,
    REG_RF_SWP_SPECVAL7,
    REG_RF_SWP_BITMAPCNT,
    REG_RF_SWP_SKIPSTART,
    REG_RF_SWP_SKIPEND,
    REG_RF_SWP_INC,
    REG_RF_SWP_SKIPSTART2,
    REG_RF_SWP_SKIPEND2 = 0x5c8/4,
    REG_RF_SPURCANCEL,
    REG_RF_RSSIMINMAX,
    REG_RF_SWP_PAUSE,
    REG_RF_SWP_ADVCDS,
    REG_RF_SWP_MAXCALCAP,
    REG_RF_SWP_MAXRSSI,
    REG_RF_FSKAMP_SEL = 0x5e8/4,
    REG_RF_SRI_SLAVE_SEL = 0x5fc/4,
    REG_RF_R_GAINLUT0 = 0x608/4,
    REG_RF_R_GAINLUT1,
    REG_RF_R_GAINLUT2,
    REG_RF_R_GAINLUT3,
    REG_RF_R_GAINLUT4,
    REG_RF_R_GAINLUT5,
    REG_RF_R_GAINLUT6,
    REG_RF_R_GAINLUT7,
    REG_RF_R_GAINLUT8,
    REG_RF_R_AGCCTRL0,
    REG_RF_R_AGCCTRL1,
    REG_RF_R_AGCSTATUS,
    REG_RF_R_RSSIDCSTATUS,
    REG_RF_R_SQUELCHCTRL,
    REG_RF_R_RXPSKCTRL0,
    REG_RF_R_RXPSKCTRL1,
    REG_RF_R_DCOFFESTCTRL0,
    REG_RF_R_DCOFFESTCTRL1,
    REG_RF_R_DCOFFESTCTRL2,
    REG_RF_R_DCOFFESTCTRL3,
    REG_RF_R_DCOFFESTCTRL4,
    REG_RF_R_DCOFFESTCTRL5,
    REG_RF_R_DEMODCTRL,
    REG_RF_R_SYNCCTRL,
    REG_RF_R_EQCOEFFCTRL0,
    REG_RF_R_EQCOEFFCTRL1,
    REG_RF_R_LOOPCOEFFCTRL0,
    REG_RF_R_LOOPCOEFFCTRL1,
    REG_RF_R_PSKSYNCWORD0,
    REG_RF_R_PSKSYNCWORD1,
    REG_RF_R_PSKSYNCWORD2,
    REG_RF_R_ADJFCCTRL,
    REG_RF_R_IFFREQ,
    REG_RF_R_DCOFFCOMPQ,
    REG_RF_R_DCOFFCOMPI,
    REG_RF_R_MODCTRL0,
    REG_RF_R_MODCTRL1,
    REG_RF_R_LOOPCOEFFCTRL2,
    REG_RF_R_LOOPCOEFFCTRL3,
    REG_RF_R_TXQPSKLUTCTRL = 0x6ac/4,
    REG_RF_R_TX8PSKLUTCTRL0,
    REG_RF_R_TX8PSKLUTCTRL1,
    REG_RF_R_TSSICTRL,
    REG_RF_R_TSSISTATUS,
    REG_RF_R_TESTCTRL,
    REG_RF_R_PA_VCTRL_CTRL,
    REG_RF_R_TXPUCTRL,
    REG_RF_R_RXPUCTRL,
    REG_RF_R_SYNTHPUCTRL,
    REG_RF_R_PARAMPCTRL = 0x6d8/4,
    REG_RF_R_VCOLOPUCTRL,
    REG_RF_R_DSADCPUCTRL,
    REG_RF_R_TRPUCTRL,
    REG_RF_R_TSSIPUCTRL,
    REG_RF_R_CLKCTRL = 0x6f0/4,
    REG_RF_R_RXPSKCTRL2,
    REG_RF_R_RXPSKCTRL3,
    REG_RF_R_RXPSKCTRL4,
    REG_RF_R_AGCCTRL2,
    REG_RF_R_REVISION,
    REG_RF_R_DCOFFCOMPQ1,
    REG_RF_R_DCOFFCOMPI1,
    REG_RF_R_DCOFFCOMPQ2,
    REG_RF_R_DCOFFCOMPI2,
    REG_RF_R_DCOFFCOMPQ3,
    REG_RF_R_DCOFFCOMPI3,
    REG_RF_R_DCOFFCOMPQ4,
    REG_RF_R_DCOFFCOMPI4,
    REG_RF_R_IQCOMP1,
    REG_RF_R_IQCOMP2,
    REG_RF_R_IQCOMP3,
    REG_RF_R_IQCOMP4,
    REG_RF_R_RXPSKPHERR1,
    REG_RF_R_RXPSKPHERR2,
    REG_RF_R_RXPSKPHERR3,
    REG_RF_R_RXPSKPHERR4,
    REG_RF_R_RXPSKPHERR5,
    REG_RF_R_RXPSKPHERR6,
    REG_RF_R_RXPSKMAGERR,
    REG_RF_R_SLNA_GAINLUT0,
    REG_RF_R_SLNA_GAINLUT1,
    REG_RF_R_SLNA_CTRL0,
    REG_RF_R_SLNA_CTRL1,
    REG_RF_R_SWP_STARTKICK,
    REG_RF_R_SWP_ENDINC,
    REG_RF_R_SWP_THRESH,
    REG_RF_R_SWP_COUNTER,
    REG_RF_R_SWP_VCOCALCAP,
    REG_RF_R_SWP_THRESHRSSI,
    REG_RF_R_SWP_SPECVAL0,
    REG_RF_R_SWP_SPECVAL1,
    REG_RF_R_SWP_SPECVAL2,
    REG_RF_R_SWP_SPECVAL3,
    REG_RF_R_SWP_SPECVAL4,
    REG_RF_R_SWP_SPECVAL5,
    REG_RF_R_SWP_SPECVAL6,
    REG_RF_R_SWP_SPECVAL7,
    REG_RF_R_SWP_BITMAPCNT,
    REG_RF_R_SWP_SKIPSTART,
    REG_RF_R_SWP_SKIPEND,
    REG_RF_R_SWP_INC,
    REG_RF_R_SWP_SKIPSTART2,
    REG_RF_R_SWP_SKIPEND2 = 0x7c8/4,
    REG_RF_R_SPURCANCEL,
    REG_RF_R_RSSIMINMAX,
    REG_RF_R_SWP_PAUSE,
    REG_RF_R_SWP_ADVCDS,
    REG_RF_R_SWP_MAXCALCAP,
    REG_RF_R_SWP_MAXRSSI,
    REG_RF_R_FSKAMP_SEL = 0x7e8/4,
    REG_RF_R_SRI_SLAVE_SEL = 0x7fc/4,
    REG_RF_COUNT
};

struct Rf : Peripheral<REG_RF_COUNT>
{
    /// Constructor
    Rf(sc_core::sc_module_name name)
    : Peripheral<REG_RF_COUNT>(name)
    {
        // initialize the registers content
    }

private:
    /** Register read function
     * @param[in] offset Offset of the register to read
     * @return The value read
     */
    uint32_t
    reg_rd(uint32_t offset);

    /** Register write function
     * @param[in] offset Offset of the register to read
     * @param[in] offset Value to write in the register
     */
    void
    reg_wr(uint32_t offset, uint32_t value);

};

#endif /*RF_H_*/
